High density packaging technologies have been developed to increase the degree of integration of integrated circuit devices. As illustrated by FIGS. 1-2, chip fabrication technologies have been developed to support packaging of multi-chip stacks within a single package. In particular, FIGS. 1-2 illustrate an integrated circuit wafer 11 that may be diced into a plurality of integrated circuit chips 50. Each chip 50 includes a plurality of chip pads 12 (e.g., I/O pads) on one surface of a chip 50 and rerouting conductors 21, which support rerouting of signals from corresponding chip pads 12 to an opposite surface of the chip 50. These rerouting conductors 21 pass through via holes 15, which may extend adjacent a periphery of each chip 50. The via holes 15 are provided in a spacing region S, which extends in a grid-like pattern between the chips 50. Scribe lines 51 extend in the center of this grid-like pattern S. These scribe lines 51 identify the placement of a cutting tool 29 when the wafer 11 is being diced into separate chips 50. To inhibit the likelihood of damage during a dicing step, the width of the spacing regions S may need to be relatively large. Unfortunately, the use of relatively wide spacing regions S can lead to a decrease in the number of chips within each wafer 11.